Audio Video Bridging & Time-Sensitive Networking IP

The FPGA logic in DornerWorks AVB solution was developed for AMD FPGAs. As part of the AVB IP, it enables support for multiple types of heterogeneous traffic over a common network to reduce infrastructure costs.

This IP was developed for the most demanding AVB systems, including those requiring defense-class security, so you can be sure it’s right for yours.

Key Capabilities

• 1Gbs full-duplex MAC (IEEE 802.3)
• IEEE 1722 Data encapsulation for Synchronous and Asynchronous channels
• Automatic gPTP (IEEE 802.1AS-REV; slave-only)
• +/- 8 ns accuracy
• Rapid time synchronization convergence
• High precision packet prioritization and scheduling
• RGMII and SGMII interfaces with COTS PHY with MDIO
• User-configurable time-based triggers
• One PPS output signal with configurable hold-up time
• Supports 8 QoS priority levels / traffic classes, each with configurable strict-priority and credit-based scheduler (IEEE 802.1Q-2014)
• IEEE 1722 Data encapsulators connect to 3 QOS priority levels, leaving 5 open for other traffic classes
• Streaming IP with no packet buffering minimizes latency and maximizes determinism
• AMD AMBA/AXI4 Lite and Stream interface

TSN schedules transmissions by adding a timed gate schedule to each class of traffic. The strict priority schedulers only select a queue for transmission if its gate is open, though multiple gates can be open simultaneously.

This IP was developed for the most demanding systems, including those requiring defense-class security, so you can be sure it’s right for yours.

Key Capabilities

Frame Preemption – IEEE 802.1Q-2018 (formerly IEEE 802.1Qbu-2016) and IEEE 802.3br

• Allows selection of any of the QoS levels to be pre-emptible or express traffic

Time Aware Shaper – IEEE 802.1Q-2018 (formerly IEEE 802.1Qbv-2015)

• Gate Control List to control each QoS level, synchronized to PTP time
• Works with AVB Credit-Based Shaper