SDSoC Tool Exploration using AES Encryption

SDSoC Tool Exploration using AES Encryption

FPGAs provide customizable access to large performance gains from parallelization of software algorithms in programmable logic. However, because FPGA programming is a significant departure from traditional software programming, wide scale utilization of FPGA-based algorithm acceleration has been hindered by a lack of necessary expertise.

The SDSoC™ development environment aims to reduce the prerequisite expertise needed to take advantage of FPGA capabilities by facilitating the transition from software algorithm to FPGA hardware logic. This paper presents the methodology and results of accelerating software defined AES-128 CBC and CTR implementations using the SDSoC development environment.

Topics covered in this white paper:

  • SDSoC development methodology
  • Cipher Block Chain configuration with AES 128
  • SDSoC test methodology
  • Hardware Accelerating AES 128 with CBC Mode

Download these resources and learn about using the SDSoC tool with AES encryption.


Contributing authors

Anthony BoorsmaAnthony Boorsma
Anthony helps empower DornerWorks’ exceptional engineering talent to provide high-quality engineering services and solutions that consistently exceed expectations. He works with clients throughout the development process, keeping them updated on their project’s progress and goals.
Jeff VanOss HeadshotJeff VanOss
Jeff VanOss is a former DornerWorks embedded engineer.